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HV7131RP
CMOS Image Sensor with Image Signal Processing
HV7131RP
MagnaChip Semiconductor Ltd.
Version 1.5
2005/ 02 / 04 V1.5 -12005 MagnaChip Semiconductor Ltd.
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HV7131RP
Revision History
Revision V1.0 V1.1 V1.2 V1.3 Script Date 2003/10/15/Wed 2004/01/20/Tue 2004/03/22/Mon 2004/08/16/Mon Comments - HV7131RP Preliminary is released - register information is updated - register information is updated - register information is updated. (AE Anti-Flicker Step, AE Maximum Limit) - ENB setting is updated. V1.4 V1.5 2004/10/04/Mon 2005/02/04/Fri - MagnaChip Logo Changed - Spectral response is updated. (p.13) - Anti-Banding Configuration is updated.(p.62) - Output Data according to Video Mode is updated.(p. 63) - Electro-Optical Characteristics is updated.(p.75)
Copyright by MagnaChip Semiconductor Ltd., all right reserved 2003, 2004, 2005
Disclaimer
This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd., assumes no responsibility or liability arising from use of circuit described, and no patent licenses are implied.
2005/ 02 / 04 V1.5 -22005 MagnaChip Semiconductor Ltd.
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HV7131RP
CONTENTS
General Description ...........................................................................................................................4 Features ..............................................................................................................................................4 Block Diagram ....................................................................................................................................5 40LD Pin Diagram...............................................................................................................................7 Pin Description ...................................................................................................................................8 Functional Description.......................................................................................................................9 Pixel Architecture ................................................................................................................. 9 ENB Setting guide information for normal stand-by mode ............................................... 9 Sensor Imaging Operation..................................................................................................10 10bit on-chip ADC ...............................................................................................................10 Gamma Correction ..............................................................................................................11 Color Interpolation ..............................................................................................................11 Color Correction & Color Space Conversion.....................................................................12 Image Enhancement............................................................................................................12 Edge Enhancement .............................................................................................................12 Output Formatting...............................................................................................................12 Auto Exposure Control .......................................................................................................13 Auto White Balance .............................................................................................................13 Spectral Characteristics......................................................................................................13 Register Description ........................................................................................................................14 Frame Timing.....................................................................................................................................57 Anti-Banding Configuration.................................................................................................................63 Data Output Timing and Interface ...................................................................................................63 Output Data according to Video Mode............................................................................................64 I2C Chip Interface.............................................................................................................................72 AC/DC Characteristics......................................................................................................................73 Electro-Optical Characteristics........................................................................................................77 CLCC Package Specification ..............................................................................................78
2005/ 02 / 04 V1.5 -32005 MagnaChip Semiconductor Ltd.
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HV7131RP
General Description
HV7131RP is a highly integrated single chip CMOS color image sensor implemented by proprietary MagnaChip 0.30um CMOS sensor process realizing high sensitivity and wide dynamic range. Total Pixel Array are 660x507 pixels. Each active pixel composed of 4 transistors has a micro-lens to enhance sensitivity, and converts photon energy to analog pixel voltage. On-chip 10bit Analog to Digital Converter (ADC) digitizes analog pixel voltage, and on-chip Correlated Double Sampling (CDS) scheme reduces Fixed Pattern Noise (FPN) dramatically. General image processing functions such as gamma correction, color interpolation, color correction, color space conversion, H/V Edge Enhancement, Image Enhancement, auto exposure, and auto white balance are implemented to diversify its applications, and various output formats are supported for the sensor to easily interface with different video codec chips. The integration of sensor function and image processing functions make HV7131RP especially very suitable for mobile imaging systems such as IMT-2000 phone's video part that requires very low power and system compactness.
Features
n n n n n n n n n n n n n n n n n n 1/4.5 inch optical format Total pixel array : 660x507 Active pixel array : 640x480 5.04um x 5.04um active square pixel Micro-lens for high sensitivity RGB mosaic color filter array On-chip 10 bit ADC Correlated double sampling for reduction of Fixed Pattern Noise Black Level Compensation Gamma correction by programmable piecewise linear approximation 3x3 Color interpolation Color correction by programmable 3x3 matrix operation Image Enhancement : Contrast, Hue, Saturation, Brightness Edge Enhancement Color space conversion from RGB to YCbCr Inverse Color Space conversion YCbCr to RGB Sub-sampling Modes : 2x2, 2x6, CIF, QCIF Various output formats : YCbCr 4:2:2, RGB 5:6:6, Bayer 2005/ 02 / 04 V1.5 -42005 MagnaChip Semiconductor Ltd.
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HV7131RP
n n n n n n n
8bit Data Bus Mode Automatic Exposure Control Automatic White Balance Control Frame Rate : 30 f/s at 25Mhz, HBLANK = 208, VBLANK = 8 Power Consumption: 86mW @ 30f/s and 2.8V, 68mW @ 15f/s and 2.8V, 336uW @ power down Operation Voltage Range : 2.6V ~ 3.0V, Operation Temperature : -10 ~ +50 degrees Celsius Package Types : CLCC 40 PIN, COB(Chip-on-Board), COF(Chip-on-Flex)
Block Diagram
CEN RESETB MCLK Strobe SCK SDA
Integration Time & Pre -Amp Gain Control (AE) R(G)B (Analog) Gain Control (AWB)
HSYNC VSYNC VCLK YCbCr or RGB Output Stream
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Sensor Control Logic Sensor Control Logic Sensor Control Logic Sensor Control Logic
Gamma Correction Gamma Correction Gamma Correction Gamma Correction
Sensor Core 10Bit ADC Analog Analog Pre R/G/B Gain Amp. Gain Amp.
Auto Exposure Anti Flicker Auto White Balance Color Space Conversion & Color Correction
Output Formatter & Inverse conversion
Image Enhancement (Hue, Saturation, Contrast, Brightness)
Auto Black Level Auto Black Level Auto Black Level Auto Black Level Compensation
RGB Bayer
Color Suppression H/V Edge Enhancement
Dark Noise Dark Noise Dark Noise Dark Noise Cancellation
3x3 Color Interpolation to 24bit RGB
HV7131RP
Pixel Array Structure
Metal Shielded Black Level Array [2 line] G B R G G B R G .... .... GG BG R G G B R G
G B
R G
G B
R G
.... ....
GG BG
R G
G B
R G
Metal Shielded Black Level Array [2 line]
Note: If black level data output is enabled& ABLC enabled(SCTRC[1:0] set to 2'b11) with Bayer mode select(SCTRC[7] set to high), data output in the areas of Metal Shielded Black Level Array can be monitored during 4 line period of HSYNC right after VSYNC goes from high state to low state.
2005/ 02 / 04 V1.5 -62005 MagnaChip Semiconductor Ltd.
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HV7131RP
40LD Pin Diagram
NC 5 NC 4 NC 3 NC 2 NC 1 NC NC NC NC NC 35 GND_D 34 VDD_D 33 GND_A
40 39 38 3 7 36
GND_IO 6 Y[7] 7 Y[6] 8 Y[5] 9 Y[4] 10 Y[3] 11 Y[2] 12 Y[1] 13 Y[0] 14 VDD_IO 15
HV7131GP HV7131RP CLCC 40 PIN
CLCC 40 PIN Top View Top View
32 VDD_A 31 GND_A 30 VDD_A 29 CEN 28 RESETB 27 NC 26 VDD_IO
16 17 18 19 20 21 22 23 24 25 GND_D VDD_D MCLK VSYNC HSYNC VCLK SDA SCK STROBE GND_IO
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HV7131RP
Pin Description
Pin 1-5 6 7~14 15 16 17 18 19
Type N G O P G P I O
Symbol NC GND_IO Y[7:0] VDD_IO GND_D VDD_D MCLK VSYNC No Connection Ground for I/O Buffer 8Bits Video Data output Power for I/O Buffer
Description
Ground for Internal Digital Block Power for Internal Digital Block Master Input Clock Video Frame Synchronization signal. VSYNC is active at start of image data frame.
20
O
HSYNC
Video Horizontal Line Synchronization signal. Image data is valid, when HSYNC is high.
21 22 23 24 25 26 27 28 29
O B I O G P N I I
VCLK SDA SCK STROBE GND_IO VDD_IO NC RESETB CEN
Video Output Clock I2C Standard data I/O port I2C Clock Input Strobe Signal Output Ground for I/O Buffer Power for I/O Bufrfer No Connection Sensor Reset, Low Active Chip Enable, High Active CEN low : sleep mode, CEN high : normal operation mode
30 31 32 33 34 35 36-40
P G P G P G N
VDD_A GND_A VDD_A GND_A VDD_D GND_D NC
Power for Internal Analog Block Ground for Internal Analog Block Power for Internal Analog Block Ground for Internal Analog Block Power for Internal Digital Block Ground for Internal Digital Block No Connection
2005/ 02 / 04 V1.5 -82005 MagnaChip Semiconductor Ltd.
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HV7131RP
Functional Description
Pixel Architecture
Pixel architecture is a 4 transistor NMOS pixel design. The additional use of a dedicated transfer transistor in the architecture reduces most of reset level noise so that fixed pattern noise is not visible. Furthermore, micro-lens is placed upon each pixel in order to increase fill factor so that high pixel sensitivity is achieved.
ENB Setting guide information for normal stand-by mode
It is necessary that this kind of initialization sequence for the normal stand-by mode of HV7131RP after system power on
System power On More than 4cycle Sensor operation sequence Sensor Power down sequence
DVDD/AVDD
RESETB
Low
MCLK
Low 1'st VSYNC out
VSYNC
Low 2.0 [Mcycle] for 1'st VSYNC out
ENB
Low 2.086 [Mcycle] for logic stable time
I2C Video stream Don't care Initialization sequence Don't care Camera Mode
ex) If MCLK = 25[Mhz] => 2.086[Mcycle] / 25[MHz] = 83.44 ms The time period of ENB high value have to keep for 83.44[ms] or more
2005/ 02 / 04 V1.5 -92005 MagnaChip Semiconductor Ltd.
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HV7131RP
Sensor Imaging Operation
Imaging operation is implemented by the offset mechanism of integration domain and scan domain (rolling shutter scheme). First integration plane is initiated, and after the programmed integration time is elapsed, scan plane is initiated, then image data start being produced.
Time
Integration Plane Frame 0 Scan Integration Plane Frame 1 Scan Plane Frame 1 Frame 1 Time Plane Frame 0 Frame 0 Time Integration Time
10bit on-chip ADC
On-chip ADC converts analog pixel voltage to 10bit digital data.
2005/ 02 / 04 V1.5 - 10 2005 MagnaChip Semiconductor Ltd.
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HV7131RP
Gamma Correction
Piecewise linear gamma approximation method is implemented. Ten piece linear segments are supported and user-programmable. Gamma Slope Registers are programmed as the integer value of real slope value that is multiplied by 64.
Out Start 9 : : Start 3 Start 2 Slope 1 Start 1 Slope 0 Start 0 0 4 16 32 64 128 192 256 512 768 1023 In
Gamma Transfer Function
Color Interpolation
3x3 linear color interpolation is done by moving 3x3 interpolation window by one pixel horizontally and vertically
B
G R G
B
G B
G B
R G
B
2005/ 02 / 04 V1.5 - 11 2005 MagnaChip Semiconductor Ltd.
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HV7131RP
Color Correction & Color Space Conversion
Both of Color Correction and Color Space conversion are implemented by 3x3 matrix operation, so that two stages may be merged into one matrix stage. Color correction matrix may be resolved by measuring sensor's color spread characteristics for primary color source and calculating the inverse matrix of color spread matrix. For color space conversion matrix, the equation from CCIR-601 standard is normally used. Therefore, the intended single matrix for color correction and color space conversion may be resolved as below. Intended single matrix = Color Space Conversion Matrix * Color Correction Matrix Intended single matrix coefficients are programmable from -127/64 to 127/64. Programming register value for intended single matrix coefficients should be resolved by the following equations. For positive values, CMAxx = Integer (Real Coefficient Value x 64); For negative values, CMAxx = Two Complement(Integer (Real Coefficient Value x 64)); Real Coefficient Value values from -127/64 to 127/64 can be programmed.
CCIR-601 YCbCr color space conversion equation < Conversion Equation > Y = (77R + 150G + 29B)/256 Range: 16 ~ 235 Cb = (-44R -87G + 131B)/256 + 128 Range: 16 ~ 240 Cr = (131R - 110G - 21B)/256 + 128 Range: 16 ~ 240 < Reverse Conversion > R = Y + 1.371(Cr - 128) G = Y - 0.698(Cr - 128) - 0.336(Cb - 128) B = Y + 1.732(Cb - 128) In the above equations, R, G, and B are gamma-corrected values.
Image Enhancement
Contrast, brightness, hue and saturation are programmable. Contrast and saturation factor range is 0.0 ~ 1.99. Brightness factor range is -127 ~ + 128. Hue factor range is -30~ + 30.
Edge Enhancement
Edge enhancement is performed for increasing sharpness of image. Edge weight range is 0.5 ~ 8.0.
Output Formatting
The output formats such as Bayer Raw Data, RGB 5:6:5, and YCbCr 4:2:2 are supported and the sequence of Cb and Cr are programmable.
2005/ 02 / 04 V1.5 - 12 2005 MagnaChip Semiconductor Ltd.
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HV7131RP
Auto Exposure Control
Y mean value is continuously calculated every frame, and the integration time value is increased or decreased according to difference between target Y mean value and current frame Y mean value.
Auto White Balance
Cb/Cr frame mean value is calculated every frame and according to Cb/Cr frame mean values' displacement from Cb/Cr white target point.
Spectral Characteristics
2005/ 02 / 04 V1.5 - 13 2005 MagnaChip Semiconductor Ltd.
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HV7131RP
Register Description
Register Symbol Add. (Hex) Device ID Sensor Control A Sensor Control B Sensor Control C Row Start Address High Row Start Address Low Column Start Address High Column Start Address Low Window Height High Window Height Low Window Width High Window Width Low HBLANK Time High HBLANK Time Low VBLANK Time High VBLANK Time Low Red Color Gain Green Color Gain Blue Color Gain Preamp Gain Preamp Gain Min Preamp Gain Max Preamp Gain Nominal Analog control A Reset Clamp Red Pixel Black Offset Green Pixel Black Offset Blue Pixel Black Offset Red Pixel Active Offset Green Pixel Active Offset DEVID SCTRA SCTRB SCTRC RSAU RSAL CSAU CSAL WIHU WIHL WIWU WIWL HBLU HBLL VBLU VBLL RCG GCG BCG PgaVal PgaMIN PgaMAX PgaNOM ACTRA ACTRB ORedl OGrnl OBlul ORedU OGrnU 00 01 02 03 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 21 22 23 24 25 Default (Hex) 42 23 00 01 00 02 00 02 01 e0 02 80 00 d0 00 08 18 18 18 20 14 ff 20 37 7f 3f 3f 3f RO RO Product ID, Revision No. Xflip, Yflip, CIF mode, SSSel, Vmode[1:0] Power down, Clock division Sensor Internal control Register Row Start Address Upper Byte Row Start Address Lower Byte Column Start Address Upper Byte Column Start Address Lower Byte Window Height Address Upper Byte Window Height Address Lower Byte Window Width Address Upper Byte Window Width Address Lower Byte HBLANK Time 208 clocks VBLANK Time 5 Lines 0.5 to 2 64 step 6bit resolution 0.5 to 2 64 step 6bit resolution 0.5 to 2 64 step 6bit resolution 0.5 to 16.5 256 step 8bit resolution 0.5 to 16.5 256 step 8bit resolution 0.5 to 16.5 256 step 8bit resolution 0.5 to 16.5 256 step 8bit resolution Amp Bias[3:0], CDS bias[6:4] Reset Clamping[7:4], ADC bias[3:0] -127 to +127 256 step MSB = `0' mean "-" {1'b0, [4:0]} LSB = `1' mean "+" {1'b0, [4:0]} ADC Offset Value for Active Red Pixel ADC Offset Value for Active Green Pixel Description
2005/ 02 / 04 V1.5 - 14 2005 MagnaChip Semiconductor Ltd.
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HV7131RP
Blue Pixel Active Offset Black Level Threshold ISP Function Enable ISP Output Format Dark Noise Cancellation
OBluU BLCTH IspFen OutFmT DncMode
26 27 30 31 33
RO 3f 02 60 41
ADC Offset Value for Active Blue Pixel Black Level Threshold Value(256) Functions Enable & Edge Eh Image data output formatting & Inversion Dnc Blocking[7:4], Dnc Th[3:2], Dnc Mode[1:0]
Dnc Enable Gain Dnc Enable Int. Time
DncGain DncIntH DncIntM
34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f
3e 13 12 2f db F6 0f 28 08 f5 ce 3d 00 04 12 21 37 55 6b 7d B4 dd 40 4b 3c 2c 1e 16
Dnc enable at Pgain 4.3x Dnc enable at Int time > {DncIntH, DncIntM, 8'h00} Color matrix coefficient 11 Color matrix coefficient 12 Color matrix coefficient 13 Color matrix coefficient 21 Color matrix coefficient 22 Color matrix coefficient 23 Color matrix coefficient 31 Color matrix coefficient 32 Color matrix coefficient 33 Start point for gamma line segment 0 Start point for gamma line segment 1 Start point for gamma line segment 2 Start point for gamma line segment 3 Start point for gamma line segment 4 Start point for gamma line segment 5 Start point for gamma line segment 6 Start point for gamma line segment 7 Start point for gamma line segment 8 Start point for gamma line segment 9 Slope value for gamma line segment 0 Slope value for gamma line segment 1 Slope value for gamma line segment 2 Slope value for gamma line segment 3 Slope value for gamma line segment 4 Slope value for gamma line segment 5
Color Matrix Coefficient 11 Color Matrix Coefficient 12 Color Matrix Coefficient 13 Color Matrix Coefficient 21 Color Matrix Coefficient 22 Color Matrix Coefficient 23 Color Matrix Coefficient 31 Color Matrix Coefficient 32 Color Matrix Coefficient 33 Gamma Segment Point 0 Gamma Segment Point 1 Gamma Segment Point 2 Gamma Segment Point 3 Gamma Segment Point 4 Gamma Segment Point 5 Gamma Segment Point 6 Gamma Segment Point 7 Gamma Segment Point 8 Gamma Segment Point 9 Gamma Segment Slope 0 Gamma Segment Slope 1 Gamma Segment Slope 2 Gamma Segment Slope 3 Gamma Segment Slope 4 Gamma Segment Slope 5
CMA11 CMA12 CMA13 CMA21 CMA22 CMA23 CMA31 CMA32 CMA33 GmaP0 GmaP1 GmaP2 GmaP3 GmaP4 GmaP5 GmaP6 GmaP7 GmaP8 GmaP9 GmaS0 GmaS1 GmaS2 GmaS3 GmaS4 GmaS5
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HV7131RP
Gamma Segment Slope 6 Gamma Segment Slope 7 Gamma Segment Slope 8 Gamma Segment Slope 9 Invers Color constant for R Invers Color constant for G Invers Color constant for G Invers Color constant for B Hue Value 1 Hue Value 2 Contrast Value Brightness Value Saturation Value Edge Weight Control Value Edge Low Enhancement
GmaS6 GmaS7 GmaS8 GmaS9 RCrconst GCrconst GCbconst BCbconst HUE1 HUE2 Contrast Brightness Saturation EgWtCon
50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e
12 0e 0a 09 57 d4 eb 6e 00 80 80 00 80 00 10
Slope value for gamma line segment 6 Slope value for gamma line segment 7 Slope value for gamma line segment 8 Slope value for gamma line segment 9 Invers Color Constant for R Invers Color Constant for G Invers Color Constant for G Invers Color Constant for B Hue value 1 Hue value 2 Contrast Value Brightness Value Saturation Value Edge Weight Control Value Edge Enhancement Vth Low
Vth EdThLo
Suppression Pre Amp Gain SupGMin Min Saturation Pre Amp Gain SatGMin Min Edge Pre Amp Gain Min AE Mode 1 AE Mode 2 AE Windows weight Integration Time High Integration Time Middle Integration Time Low AE Target OutDoor AE Target InDoor AE Lock Boundary EdgGMin AeMode1 AeMode2 AeWinWgt INTH INTM INTL LuTarget1 LuTarget2 AeLockFineBn d AE Unlock Boundary AE Anti-Flicker Step High AE Anti-Flicker Step Middle AeUnlockBnd AeintStepH AeintStepM
60
24
Suppression Pre Amp Gain Min
61
24
Saturation Pre Amp Gain Min
62 70 71 72 73 74 75 76 77 78
24 29 ed cd 02 71 00 5a 5a f6
Edge Gain Min Auto exposure mode selection 1 Auto exposure mode selection 2 AE Windows weigth Integration Time High Integration Time Middle Integration Time Low AE Target OutDoor AE Target InDoor AE Lock Boundary
79 7a 7b
2a 01 38
AE Unlock Boundary AE Anti-Flicker Step High AE Anti-Flicker Step Middle
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HV7131RP
AE Anti-Flicker Step Low AE Maximum Limit High AE Maximum Limit Middle AE Maximum Limit Low AWB Mode AWB Windows Weight AWB Cb Target Position AWB Cr Target Position AWB Lock Boundary AWB Unlock Boundary AWB Cb White Pixel
AeintStepL AeIntLimitH AeIntLimitM AeIntLimitL AWBMode AwbWinWgt CbTarget CrTarget AwbLockBnd AwbUnlockBnd CbWhiteBnd
7c 7d 7e 7f 80 82 83 84 85 86 87
80 09 c4 00 18 00 80 80 02 20 30
AE Anti-Flicker Step Low AE Maximum Limit High AE Maximum Limit Middle AE Maximum Limit Low AWB mode AWB Windows Weight AWB Cb Target Position AWB Cr Target Position AWB Lock Boundary AWB Unlock Boundary AWB White Pixel Boundary
Boundary AWB Cr White Pixel CrWhiteBnd 88 30 AWB White Pixel Boundary
Boundary AWB C Boundary R/B Gain Max R/B Gain Min AE State Machine AWB State Machine Lu Frame Mean Cb Frame Mean Cr Frame Mean Anti Banding Gain Min Anti Banding Gain Max Awb White Pixel Boundary Awb Black Pixel Boundary Awb Valid Number Integreation-Scan Offset High Integreation-Scan Offset Middle Integreation-Scan Offset Low Plane IntScnOfsL 98 R0 Integration-Scan Plane Offset Low Plane IntScnOfsM 97 R0 Integration-Scan Plane Offset Middle AwbCBnd AwbGainMax AwbGainMin AeFSM AwbFSM LuFMean CbFMean CrFMean KlBndMin KlBndMax AwbWhite AwbBlack AwbNumber Plane IntScnOfsH 89 8a 8b 8c 8d 8e 8f 90 91 92 93 94 95 96 30 3f 00 RO RO RO RO RO 14 3d ff 00 02 R0 AWB Cb+Cr Boundary R/B Gain Max R/B Gain Min AE State Machine AWB State Machine Lu Frame Mean Value Cb Frame Mean Value Cr Frame Mean Value Anti Banding Pre Amp Gain Min Anti Banding Pre Amp Gain Max Awb White Pixel Boundary Awb Black Pixel Boundary Awb Valid Number Integration-Scan Plane Offset High
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HV7131RP
Device ID [DEVID : 00h : 42h]
7 6 5 4 3 2 1 0
Product ID 0 1 0 0 0
Revision Number 0 1 0
High nibble represents Sensor Array Resolution, Low Nibble represents Revision Number.
Sensor Control A [SCTRA : 01h : 23h]
7 6 5 4 3 2 1 0
Reserved 0 0
X-Flip 1
Y-Flip 0
CifMode 0
SSSel 0
Video Mode 1 1
X-Flip Y-Flip CifMode
Image is horizontally flipped Image is vertically flipped When this register set to high and video mode(SCTRA[1:0]) set to "11" or "00", output data is CIF format. And if this register set to high and video mode(SCTRA[1:0]) set to "10", output data is QCIF format.
SSSel
0 1
ISP Sub-Sampling( High Image Quality, 1x Core Frame Rate) Bayer Sub Sampling( Low Image Quality, 2x Core Frame Rate) * only applicable Row, Column is always ISP
Video Mode
11 10 01 00
No Scaling mode 2x2 subsampling mode (1/4 subsampling) 2x6 subsampling mode (1/16 subsampling) No Scaling mode
* More detailed information is available on page 63
2005/ 02 / 04 V1.5 - 18 2005 MagnaChip Semiconductor Ltd.
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HV7131RP
Sensor Control B [SCTRB : 02h : 00h]
7 6 5 4 3 2 1 0
AE/AWB Block Sleep
Data path Block Sleep
Analog Block Sleep
All Internal Block Sleep
Strobe Signal Enable
Clock Division
0
0
0
0
0
0
0
0
< Clock Acronym Definition > MCF : Master Clock Frequency SCF : Sensor Clock Frequency VCF : Video Clock Frequency < Clock Frequency Relation > MCF : MCF SCF : DCF/2 DCF : MCF/Clock Division ICF SCF for 3x3 interpolation, DCF : Divided Clock Frequency ICF : Image Processing Clock Frequency LCF : Line Clock Frequency
SCF/2 for 1/4 subsampling mode SCF/4 for 1/16 subsampling mode VCF : ICF*2 for 8bit output LCF : 1/(HBLANK Period + HSYNC Period)
AE/AWB Block Sleep
AE/AWB block goes into sleep mode with this bit set to high.
Data path Block Sleep Image processing data path block goes into sleep mode with this bit set to high. Analog Block Sleep all internal analog block goes into sleep mode with this bit set to high. With All Digital Block Sleep active, sensor goes into power down mode. All Internal Block Sleep Strobe Signal Enable When strobe signal is enabled by this bit, STROBE pin will indicates when strobe light should be splashed in the dark environment to get adequate lighted image. Clock Division divides input master clock(IMC) for internal use. Internal divided clock frequency (DCF) is defined as master clock frequency (MCF) divided by specified clock divisor. Internal divided clock frequency (DCF) is as follows. 000 : MCF, 2005/ 02 / 04 V1.5 - 19 2005 MagnaChip Semiconductor Ltd. 001 : MCF/2, 010 : MCF/4, 011 : MCF/8 all internal digital and analog block goes into sleep with this bit set to high.
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HV7131RP
100 : MCF/16,
101 : MCF/32,
110 : MCF/64,
111 : MCF/128
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HV7131RP
Sensor Control C [SCTRC : 03h : 01h]
7 6 5 4 3 2 1 0
Bayer Output Enable
Single Shot Mode
Black level average output
HSYNC in VBLANK
reserved
Unit Gain Mode
Black Level Data Enable
ABLC enable
0
0
0
0
0
0
0
1
Bayer Output Enable
0
Output format is set to RGB565 or YCbCr 4:2:2 by ISP Output Format [31h] value.
1 Single Shot Mode Black Level Average Output 1
Bayer Raw data which does not pass ISP function is printed out.
With this register set to high, single video image is streamed out 0 This bit enable R/G/B Active Offset registers[24h-26h] to represent updated active offset values This bit enable R/G/B Active Offset registers[24h-26h] to represent black level average value
HSYNC in VBLANK
VBLANK is equivalent to VSYNC, and HSYNC is the inversion of HBLANK, and this bit control whether HSYNC is active or not when VBLANK unit is LCF.
VSYNC (VBLANK) HSYNC
Unit Gain Mode
If set to HIGH, the value of R Gain and B Gain will become equal to G Gain.
Black Level Data Enable Auto Black Level Compensation
HSYNC is generated for light-shielded pixels in 4 lines.
Black level average values of light-shielded pixels are compensated when active image data is produced.
2005/ 02 / 04 V1.5 - 21 2005 MagnaChip Semiconductor Ltd.
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HV7131RP
Row Start Address High [RSAU : 08h : 00h]
7 6 5 4 3 2 1 0
reserved
Row Start Address High
0
0
0
0
0
0
0
0
Row Start Address Low [RSAL : 09h : 02h]
7 6 5 4 3 2 1 0
Row Start Address Low 0 0 0 0 0 0 1 0
Row Start Address register defines the row start address of image read out operation.
Column Start Address High [CSAU : 0ah : 00h]
7 6 5 4 3 2 1 0
reserved
Column Start Address High
0
0
0
0
0
0
0
0
Column Start Address Low [CSAL : 0bh : 02h]
7 6 5 4 3 2 1 0
Column Start Address Low 0 0 0 0 0 0 1 0
Column Start Address register defines the column start address of image read out operation.
2005/ 02 / 04 V1.5 - 22 2005 MagnaChip Semiconductor Ltd.
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HV7131RP
Window Height High [WIHU : 0ch : 01h]
7 6 5 4 3 2 1 0
reserved
Window Height High
0
0
0
0
0
0
0
1
Window Height Low [WIHL : 0dh : e0h]
7 6 5 4 3 2 1 0
Window Height Low 1 1 1 0 0 0 0 0
Window Height register defines the height of image to be read out.
Window Width High [WIWU : 0eh : 02h]
7 6 5 4 3 2 1 0
reserved 0 0 0 0 0 0
Window Width High 1 0
Window Width Low [WIWL : 0fh : 80h]
7 6 5 4 3 2 1 0
Window Width Low 1 0 0 0 0 0 0 0
Window Width Address register defines the width of image to be read out.
2005/ 02 / 04 V1.5 - 23 2005 MagnaChip Semiconductor Ltd.
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HV7131RP
HBLANK Time High [HBLU : 10h : 00h]
7 6 5 4 3 2 1 0
HBLANK Time High 0 0 0 0 0 0 0 0
HBLANK Time Low [HBLL : 11h : d0h]
7 6 5 4 3 2 1 0
HBLANK Time Low 1 1 0 1 0 0 0 0
HBLANK Time register defines data blank time between current line and next line by using Sensor Clock Period unit (1/SCF), and should be larger than 208(d0h).
VBLANK Time High[VBLU : 12h : 00h]
7 6 5 4 3 2 1 0
VBLANK Time High 0 0 0 0 0 0 0 0
VBLANK Time Low[VBLL : 13h : 08h]
7 6 5 4 3 2 1 0
VBLANK Time Low 0 0 0 0 1 0 0 0
VBLANK Time register defines active high duration of VSYNC output. Active high VSYNC indicates frame boundary between continuous frames. For VSYNC-HSYNC timing relation in the frame transition, please refer to Frame Timing section.
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Each sensor has a little different photo-diode characteristics so that the sensor provides internal adjustment registers that calibrate internal sensing circuit in order to get optimal performance. Sensor characteristics adjustment registers are as below.
Red Color Gain [RCG : 14h : 18h]
7 6 5 4 3 2 1 0
reserved 0 0 0 1
R Color Gain 1 0 0 0
Green Color Gain [RCG : 15h : 18h]
7 6 5 4 3 2 1 0
reserved 0 0 0 1
G Color Gain 1 0 0 0
Blue Color Gain [RCG : 16h : 18h]
7 6 5 4 3 2 1 0
reserved 0 0 0 1
B Color Gain 1 0 0 0
There are three color gain registers for R, G, B pixels, respectively. Programmable range is from 0.5X ~ 2.5X. Effective Gain = 0.5 + B<5:0>/32. These registers may be used for white balance and color effect with independent R,G,B color control. Default gain is 1.25X.
Preamp Gain [PgaVal : 17h : 20h]
7 6 5 4 3 2 1 0
Preamp Gain 0 0 1 0 0 0 0 0 Preamp Gain is common gain for R, G, B channel and used for auto exposure control. Programmable range is from 0.5X ~ 16.5X. Default gain is 2.5X. Gain = 0.5 + B<7:0>/16
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Preamp Gain Min [PgaMin : 18h : 14h]
7 6 5 4 3 2 1 0
Preamp Gain Min 0 0 0 1 0 1 0 0
Preamp Gain Min is minimum value of preamp gain when sensor adjusts pre-amplifier gain for auto exposure control. Programmable range is same as preamp gain. Recommended value is 0.5X.
Preamp Gain Max [PgaMax : 19h : ffh]
7 6 5 4 3 2 1 0
Preamp Gain Max 1 1 1 1 1 1 1 1
Preamp Gain Max is maximum value of preamp gain when sensor adjusts preamp gain for auto exposure control. Programmable range is same as preamp gain. Recommended value is 16.5X.
Preamp Gain Normal [PgaNom : 1ah : 20h]
7 6 5 4 3 2 1 0
Preamp Gain Normal 0 0 1 0 0 0 0 0
Preamp Gain Normal is reference value of preamp gain when sensor adjusts preamp gain for auto exposure control. First, sensor controls integration time before adjusting preamp gain for auto exposure control. After integration time is changed to the minimum or maximum value, sensor adjusts preamp gain from this register value. Programmable range is same as preamp gain. Recommended value is 1.5X.
Analog control A [ACTRA : 1bh : 37h]
7 6 5 4 3 2 1 0
reserved 0 0
Pixel Bias
Amp Bias 1 0 1 1 1
1
CDS Bias[6:4]
controls the amount of current in CDS bias circuit to amplify CDS output effectively. The larger register value increases the amount of current. controls the amount of current in internal amplifier bias circuit to amplify
Amplifier Bias[3:0]
pixel output effectively. The larger register value increases the amount of current.
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Reset Clamp [ACTRB : 1ch : 7fh]
7 6 5 4 3 2 1 0
Reset Level Clamp 0 1 1 1 1 1
ADC Bias 1 1
Reset Clamping[7:4]
Because extremely bright image like sun affects reset data voltage of pixel to lower, bright image is captured as black image in image sensor regardless of correlated double sampling. To solve this extraordinary phenomenon, we adopt the method to clamp reset data voltage. Reset Level Clamp controls the reset data voltage to prevent inversion of extremely bright image. The larger register value clamps the reset data level at highest voltage level. Default value is 7 to clamp the reset data level at appropriate voltage level.
ADC Bias[3:0]
ADC Bias controls the amount of current in ADC bias circuit to operate ADC effectively. The larger register value increases the amount of current.
Red Pixel Black Offset [ORedl : 21h : 3fh]
7 6 5 4 3 2 1 0
Red Pixel Black Offset 0 0 1 1 1 1 1 1
Green Pixel Black Offset [OGrnl : 22h : 3fh]
7 6 5 4 3 2 1 0
Green Pixel Black Offset 0 0 1 1 1 1 1 1
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Blue Pixel Black Offset [OBlul : 23h : 3fh]
7 6 5 4 3 2 1 0
Blue Pixel Black Offset 0 0 1 1 1 1 1 1
These registers control the offset voltage of ADC that changes the black level value for active pixels, red, green and blue pixel respectively. The registers are internally updated by black level compensation logic, and are read-only registers. Register bit functions are composed as follows.
Pixel Black Offset[7]
The bit specifies whether to subtract or add offset voltage in ADC input for light-shielded pixels.
Pixel Black Offset[6:0] This value specifies the amount of offset voltage for light-shielded pixels.
Red Pixel Active Offset [ORedU : 24h : RO]
7 6 5 4 3 2 1 0
Red Pixel Active Offset RO RO RO RO RO RO RO RO
Green Pixel Active Offset [OGrnU : 25h : RO]
7 6 5 4 3 2 1 0
Green Pixel Active Offset RO RO RO RO RO RO RO RO
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Blue Pixel Active Offset [OBluU : 26h : RO]
7 6 5 4 3 2 1 0
Blue Pixel Active Offset RO RO RO RO RO RO RO RO
These registers control the offset voltage of ADC that changes the black level value for active pixels, red, green and blue pixel respectively. The registers are internally updated by black level compensation logic, and are read-only registers. Register bit functions are composed as follows.
Pixel Active Offset[7] Pixel Active Offset[6:0]
The bit specifies whether to subtract or add offset voltage in ADC input for active pixels. This value specifies the amount of offset voltage for active pixels.
Black Level Threshold [BLCTH : 27h : 3fh]
7 6 5 4 3 2 1 0
Black Level Threshold 1 1 1 1 0 0 1 1
The register specifies the maximum value which determines whether light-shielded pixel output is valid. When light-shielded pixel output exceeds this limit, the pixel is not accounted for black level calculation.
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ISP Function Enable [IspFen : 30h : 02h]
7 Saturation Suppression Enable 6 Color Suppression Enable 5 IspFen[5] 4 Smooth Filter Enable 3 Edge Enhance Enable 2 Edge Algorithm Select 1 Gamma Correction 0 IspFen[0]
0
0
0
0
0
0
1
0
0
Disable It always comes to apply the same Saturation [5ch] value in a certain
Saturation Suppression Enable 1
environment. Enable. If preamp gain[17h] exceeds saturation preamp gain min[60h], saturation value[5ch] is suppressed.
Color Suppression Enable IspFen[5]
0 1
Disable Enable. Chroma Suppressed U, V output
Set `0' 0 Disable. Enable. If Edge Enhancement is carried out, a image will become very sharp so by using smooth filter we can obtain a slightly soft image. 0 Disable. Enable. In order to generate sharper image edge emphasizes and difference of the section of edge increases. This bit selects edge enhancement algorithm.
Smooth Filter Enable
1
Edge Enhance Enable
1
Edge Algorithm Select
0 1 0
Use the algorithm which makes the line of edge vivid. Use the algorithm which makes the line of edge embossing. Disable. Normal Bayer Output Enable. Gamma Corrected Bayer Output
Gamma Correction IspFen[0]
1
Set `0'
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ISP Output Format [OutFmt : 31h : 60h]
7 6 5 4 3 2 1 0
reserved
UFirst
YFirst
RGB565 Enable
Clk HSC
Inv VSC
Inv HSC
Inv VCLK
-
1
1
0
0
0
0
0
U First Y First RGB 565 Enable
U pixel in front of V pixel for output data sequence. Y pixel in front of U and V pixels for output data sequence. Data format of RGB 565 mode is composed with {R[7:3]/G[7:5]}, {G[4:2]/B[7:3]} or {B[7:3]/G[7:5]}, {G[4:2]/R[7:3]}. If OutFmt[5](YFirst) register set to low, data format changes to BGR 565.
Clk HSC
In HSYNC, VCLK is embedded, that is, HSYNC is toggling at VCLK rate during normal HSYNC time
Inv VSC Inv HSC Inv VCLK
VSYNC output polarity is inverted Do not support. VCLK output polarity is inverted
Dark Noise Cancellation [DncMode : 33h : 41h]
7 6 5 4 3 2 1 0
DNC always performing zone 0 1 0 0
Dnc Threshold
Dnc Mode Select
0
0
0
1
DNC always performing zone DNC Threshold
Dark Noise always performed when 2 neighborhood pixel values are Less then this value x8. Determines the grade judged to be noise. (Tight)11 - 10 - 01 - 00(Loose)
DNC Mode Select
10 01
Dark Noise Cancellation is always performed Dark Noise Cancellation is performed when Integration Time (73h-
75h) exceeds (DNC enable integration Time[35h-36h] *256) or Pre-Amp Gain[17h] > Dnc Gain[34h] 11, 00 Dark Noise Cancellation is turned off
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DNC Enable Gain [DncGain : 34h : 3eh]
7 6 5 4 3 2 1 0
Dnc Mode Select
0
0
1
1
1
1
1
0
If Dnc mode[33h] set to "01" and Dnc enable gain exceeds preamp gain[17h], Dnc is enabled.
DNC Enable Int. Time High [DncIntH : 35h : 13h]
7 6 5 4 3 2 1 0
Dark Noise Cancellation
0
0
0
1
0
0
1
1
DNC Enable Int. Time Mid [DncIntM : 36h : 12h]
7 6 5 4 3 2 1 0
Dark Noise Cancellation
0
0
0
1
0
0
1
0
For Dnc mode [1:0] at "01", if {DncIntH, DncIntM, and 8'h00} value is smaller than Integration Time[73h - 75 h] , Dnc will operate.
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Color Matrix Coefficients Both of Color Correction and Color Space conversion are implemented by 3x3 matrix operation, so that two stages may be merged into one matrix stage. Color correction matrix may be resolved by measuring sensor's color spread characteristics for primary color source and calculating the inverse matrix of color spread matrix. For color space conversion matrix, the equation from CCIR-601 standard is normally used. Therefore, the intended single matrix for color correction and color space conversion may be resolved as below. Intended single matrix = Color Space Conversion Matrix * Color Correction Matrix Intended single matrix coefficients are programmable from -127/64 to 127/64. Programming register value for intended single matrix coefficients should be resolved by the following equations. For positive values, CMAxx = Integer(RealCoefficientValue x 64); For negative values, CMAxx = TwoComplement(Integer(RealCoefficientValue x 64)); RealCoefficientValue values from -127/64 to 127/64 can be programmed.
CCIR-601 YCbCr color space conversion equation < Conversion Equation > Y = (77R + 150G + 29B)/256 Range: 16 ~ 235 Cb = (-44R -87G + 131B)/256 + 128 Range: 16 ~ 240 Cr = (131R - 110G - 21B)/256 + 128 Range: 16 ~ 240 < Reverse Conversion > R = Y + 1.371(Cr - 128) G = Y - 0.698(Cr - 128) - 0.336(Cb - 128) B = Y + 1.732(Cb - 128) In the above equations, R, G, and B are gamma-corrected values
Color Matrix Coefficient 11 [CMA11 : 37h : 2fh]
7 6 5 4 3 2 1 0
Color Matrix Coefficient 11 0 0 1 0 1 1 1 1
Color Matrix Coefficient 12 [CMA12 : 38h : dbh]
7 6 5 4 3 2 1 0
Color Matrix Coefficient 12 1 1 0 1 1 0 1 1
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Color Matrix Coefficient 13 [CMA13 : 39h : f6h]
7 6 5 4 3 2 1 0
Color Matrix Coefficient 13 1 1 1 1 0 1 1 0
Color Matrix Coefficient 21 [CMA21 : 3ah : 0fh]
7 6 5 4 3 2 1 0
Color Matrix Coefficient 21 0 0 0 0 1 1 1 1
Color Matrix Coefficient 22 [CMA22 : 3bh : 28h]
7 6 5 4 3 2 1 0
Color Matrix Coefficient 22 0 0 1 0 1 0 0 0
Color Matrix Coefficient 23 [CMA23 : 3ch : 08h]
7 6 5 4 3 2 1 0
Color Matrix Coefficient 23 0 0 0 0 1 0 0 0
Color Matrix Coefficient 31 [CMA31 : 3dh : f5h]
7 6 5 4 3 2 1 0
Color Matrix Coefficient 31 1 1 1 1 0 1 0 1
Color Matrix Coefficient 32 [CMA32 : 3eh : ceh]
7 6 5 4 3 2 1 0
Color Matrix Coefficient 32 1 1 0 0 1 1 1 0
Color Matrix Coefficient 33 [CMA33 : 3fh : 3dh]
7 6 5 4 3 2 1 0
Color Matrix Coefficient 33 0 0 1 1 1 1 0 1
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Gamma Segment Start Points Gamma Segment Start Points specify the start points of nine line segments for piecewise gamma approximation. Current default gamma curve is very selected for optimum gray gradation.
Gamma Segment Point 0 [GmaP0 : 40h : 00h]
7 6 5 4 3 2 1 0
Gamma Segment Point 0 0 0 0 0 0 0 0 0
Gamma Segment Point 1 [GmaP1 : 41h : 04h]
7 6 5 4 3 2 1 0
Gamma Segment Point 1 0 0 0 0 0 1 0 0
Gamma Segment Point 2 [GmaP2 : 42h : 12h]
7 6 5 4 3 2 1 0
Gamma Segment Point 2 0 0 0 1 0 0 1 0
Gamma Segment Point 3 [GmaP3 : 43h : 21h]
7 6 5 4 3 2 1 0
Gamma Segment Point 3 0 0 1 0 0 0 0 1
Gamma Segment Point 4 [GmaP4 : 44h : 37h]
7 6 5 4 3 2 1 0
Gamma Segment Point 4 0 0 1 1 0 1 1 1
Gamma Segment Point 5 [GmaP5 : 45h : 55h]
7 6 5 4 3 2 1 0
Gamma Segment Point 5 0 1 0 1 0 1 0 1
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Gamma Segment Point 6 [GmaP6 : 46h : 6bh]
7 6 5 4 3 2 1 0
Gamma Segment Point 6 0 1 1 0 1 0 1 1
Gamma Segment Point 7 [GmaP7 : 47h : 7dh]
7 6 5 4 3 2 1 0
Gamma Segment Point 7 0 11 1 1 1 0 1
Gamma Segment Point 8 [GmaP8 : 48h : b4h]
7 6 5 4 3 2 1 0
Gamma Segment Point 8 1 0 1 1 0 1 0 0
Gamma Segment Point 9 [GmaP9 : 49h : ddh]
7 6 5 4 3 2 1 0
Gamma Segment Point 9 1 1 0 1 1 1 0 1
Gamma Slope Values Gamma Slope Registers are programmed as the integer value of real slope value that is multiplied by 64.
Gamma Segment Slope 0 [GmaS0 : 4ah : 40h]
7 6 5 4 3 2 1 0
Gamma Segment Slope 0 0 1 0 0 0 0 0 0
Gamma Segment Slope 1 [GmaS1 : 4bh : 4bh]
7 6 5 4 3 2 1 0
Gamma Segment Slope 1 0 1 0 0 1 0 1 1
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Gamma Segment Slope 2 [GmaS2 : 4ch : 3ch]
7 6 5 4 3 2 1 0
Gamma Segment Slope 1 0 0 1 1 1 1 0 0
Gamma Segment Slope 3 [GmaS3 : 4dh : 2ch]
7 6 5 4 3 2 1 0
Gamma Segment Slope 3 0 0 1 0 1 1 0 0
Gamma Segment Slope 4 [GmaS4 : 4eh : 1eh]
7 6 5 4 3 2 1 0
Gamma Segment Slope 4 0 0 0 1 1 1 1 0
Gamma Segment Slope 5 [GmaS5 : 4fh : 16h]
7 6 5 4 3 2 1 0
Gamma Segment Slope 5 0 0 0 1 0 1 1 0
Gamma Segment Slope 6 [GmaS6 : 50h : 12h]
7 6 5 4 3 2 1 0
Gamma Segment Slope 6 0 0 0 1 0 0 1 0
Gamma Segment Slope 7 [GmaS7 : 51h : 0eh]
7 6 5 4 3 2 1 0
Gamma Segment Slope 7 0 0 0 0 1 1 1 0
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Gamma Segment Slope 8 [GmaS8 : 52h : 0ah]
7 6 5 4 3 2 1 0
Gamma Segment Slope 8 0 0 0 0 1 0 1 0
Gamma Segment Slope 9 [GmaS9 : 53h : 09h]
7 6 5 4 3 2 1 0
Gamma Segment Slope 9 0 0 0 0 1 0 0 1
Inverse Color Space Conversion Inverse color space conversion transforms YCbCr by RGB. It is a function only about RGB565 format. Default setting value is from CCIR-601 standard.
R = Y + A(Cr-128) G = Y - B(Cr-128) - C(Cb-128) B = Y + D(Cb-128)
A : Inverse Color constant for R[54h] B : Inverse Color constant for G[55h] C : Inverse Color constant for G[56h] D : Inverse Color constant for B[57h]
Inverse Color constant for R [RCrconst : 54h : 57h]
7 6 5 4 3 2 1 0
Inverse Color constant for R 0 1 0 1 0 1 1 1
For inverse color space conversion matrix, this register defines the constant(A) of following equation(CCIR-601 standard). R = Y + A(Cr-128)
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Inverse Color constant for G [Gcrconst : 55h : d4h]
7 6 5 4 3 2 1 0
Inverse Color constant for G 1 1 0 1 0 1 0 0
For inverse color space conversion matrix, this register defines the constant(A) of following equation(CCIR-601 standard). G = Y - A(Cr-128) - B(Cb-128)
Inverse Color constant for G [Gcrconst : 56h : ebh]
7 6 5 4 3 2 1 0
Inverse Color constant for G 1 1 1 0 1 0 1 1
For inverse color space conversion matrix, this register defines the constant(B) of following equation(CCIR-601 standard). G = Y - A(Cr-128) - B(Cb-128)
Inverse Color constant for B [Bcrconst : 57h : 6eh]
7 6 5 4 3 2 1 0
Inverse Color constant for B 0 1 1 0 1 1 1 0
For inverse color space conversion matrix, this register defines the constant(A) of following equation(CCIR-601 standard). B = Y + A(Cb-128)
Hue value 1 [HUE1 : 58h : 00h]
7 6 5 4 3 2 1 0
Hue value 1 0 0 0 0 0 0 0 0
Hue value 2 [HUE2 : 59h : 80h]
7 6 5 4 3 2 1 0
Hue value 2 1 0 0 0 0 ~ 0 +30 0 0
Hue factor for hue adjustment. Rotate angle range : -30
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* HUE1 or HUE2 value is multiplied by 128 Angle () -30 -29 -28 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15 -14 -13 -12 -11 -10 HUE1 (hex) C0 C2 C4 C6 C8 CA CC CE D1 D3 D5 D7 D9 DB DD DF E2 E4 E6 E8 EA HUE2 (hex) 6E 6F 71 72 73 74 74 75 76 77 78 79 79 7A 7B 7B 7C 7C 7D 7D 7E Angle () -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 HUE1 (hex) EC EF F1 F3 F5 F8 FA FC FE 00 02 04 06 08 0B 0D 0F 11 14 16 18 HUE2 (hex) 7E 7E 7F 7F 7F 7F 7F 7F 7F 80 7F 7F 7F 7F 7F 7F 7F 7E 7E 7E 7D Angle () 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 HUE1 (hex) 1A 1C 1E 21 23 25 27 29 2B 2D 2F 32 34 36 38 3A 3C 3E 40 HUE2 (hex) 7D 7C 7C 7B 7B 7A 79 79 78 77 76 75 74 74 73 72 71 6F 6E
Contrast value [Contrast : 5ah : 80h]
7 6 5 4 3 2 1 0
Contrast value 1 0 0 0 0 0 0 0
Contrast factor for contrast adjustment. Programmable range of Contrast value is 0.1 ~ 1.99. The Contrast value is same as Saturation value.
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Brightness value [Brightness : 5bh : 00h]
7 6 5 4 3 2 1 0
Brightness value 0 0 0 0 0 0 0 0
Brightness adjustment is performed for summing Y data and brightness value. Brightness value is two's complement and its range is -127 ~ +128. Bright Y = Y data + brightness value. For positive value, Brightness[7:0] = Two's complement(integer)
Saturation value [Saturation : 5ch : 80h]
7 6 5 4 3 2 1 0
Saturation value 1 0 0 0 0 0 0 0
Saturation adjustment is performed for multiplying Cr,Cb data by saturation value. Programmable range of saturation value is 0.1 ~ 1.99. For instance, Sat Cb,Cr = Cb,Cr data * Satuation[7:0] / 256
< Contrast & Saturation parameter > * Contrast or Saturation Value is multiplied by 128 Number 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Contrast & Saturation (hex) 0D 1A 26 33 40 4D 5A 66 73 80 Number 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.99 Contrast & Saturation (hex) 8D 9A A6 B3 C0 CD DA E6 F3 FF
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Edge Weight Control value [EgWtCon : 5dh : 00h]
7 6 5 4 3 2 1 0
Reserved 0 0 0 f -> 8 0. 0 0
Edge Weight 0 0 0
Edge weight : 0 -> 0.5 ~
Weight increases by 0.5 step and divides into 16 step.
Edge Enhancement Vth Low [EdThLo : 5eh : 10h]
7 6 5 4 3 2 1 0
Edge Enhancement Vth Low 0 0 0 1 0 0 0 0
If edge value is higher than this register value, edge enhancement is enabled.
Suppression Pre Amp Gain Min [SupGMin : 60h : 24h]
7 6 5 4 3 2 1 0
Suppression Pre Amp Gain Min 0 0 1 0 0 1 0 0
If preamp gain value is higher than this register value and Color Suppression Enable[30h] is HIGH, color suppression is enabled.
Saturation Pre Amp Gain Min [SatGMin : 61h : 24h]
7 6 5 4 3 2 1 0
Saturation Pre Amp Gain Min 0 0 1 0 0 1 0 0
If preamp gain value is higher than this register value and Saturation Suppression Enable[30h] is HIGH, saturation suppression is enabled.
Edge Pre Amp Gain Min [EgeGMin : 62h : 24h]
7 6 5 4 3 2 1 0
Edge Pre Amp Gain Min 0 0 1 0 0 1 0 0
If preamp gain value is higher than this register value and Edge Enhancement Enable[30h] is HIGH, edge suppression is enabled. Edge suppression is a function that edge weight decreases in dark 2005/ 02 / 04 V1.5 - 42 2005 MagnaChip Semiconductor Ltd.
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environment automatically.
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Auto Exposure
Y mean value is continuously calculated every frame, and the integration time value is increased or decreased according to the displacement between current frame Y mean value and target Y mean value.
FFh
AE Unlock Boundary [79h]
AE Lock Boundary [78h] 80h AE Target [76,77h] AE Lock Boundary [78h]
AE Unlock Boundary [79h]
0h Y Frame Mean
AE Mode 1 [AEMODE1 : 70h : 29h]
7 6 5 4 3 2 1 0
AEMODE1 [7]
AntiBanding Enable
AntiBanding Minimum Break
AeWinEn
Time Speed
AE Mode
0
0
1
0
1
0
0
1
AEMODE1[7]
Set `0'
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Anti-Banding Enable
When Anti-Banding is enabled, AE initializes Integration Time registers to 4 x Anti-Banding Step value, and integration increment/decrement amount is set to Anti-Banding Step value in order to remove banding noise caused by intrinsic energy waveform of light sources. Banding noise is inherent in CMOS image sensor that adopts rolling shutter scheme for image acquisition. In this mode, AE operates with very large unit, typically a reciprocal of (2 x power line frequency), so that minute integration time tuning is not liable. Therefore, this mode is recommended for only indoor use.
Anti-Banding Minimum Break
When AE is still of out lock state despite that AE preamp analog gain update value exceeds preamp minimum gain value(18h) and integration time(73h-75h) is reached to AE Anti-Banding Step(7ah-7ch), integration time(73h-75h) is broken to less than AE Anti-Banding Step(7ah-7ch).
AeWinEn
This bit uses during calculating the average of Y value at present frame for AE. When this bit is HIGH, AE Window Weight is equal. If not, calculate the average of Y using AE Window Weight.
Time Speed AE Mode
(fast)11 - 10 - 01 - 00(slow) 11 Gain-Only control mode. Only preamp gain is controlled to get optimum exposure state. 10 Time-Only control mode. Only integration time is controlled to get optimum exposure state. 01 Time-Gain control mode. integration time and preamp gain are controlled to get optimum exposure state. 00 AE function is disabled
AE Mode 2 [AEMODE2 : 71h : edh]
7 6 5 4 3 2 1 0
Gain Speed 1
Gain Speed 2
Time Fine
Gain Fine 1
EnDGain
EnAGain
1
1
1
0
1
0
1
Gain Speed1
This Speed Only worked from dark luminance condition to white luminance condition rapidly. (fast)11 - 10 - 01 - 00(slow)
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Gain Speed2
It's about situation except the case of Gain Speed 1. Gain update speed is specified as follows. (fast)11 - 10 - 01 - 00(slow)
Integration Time Fine Tune Preamp Gain Fine Tune Enable Digital Gain
Integration time fine tuning is performed when AE arrive around AE Fine Tune Boundary to settle into AE lock state smoothly. Preamp gain fine tuning is performed when AE arrive around AE Fine Tune Boundary to settle into AE lock state smoothly. If Pre-Amp Gain(17h) is less then Anti-Banding Gain Min(91h), Bayer pixel value are gained by ratio of Anti-Banding Gain Min / Pre-Amp Gain when this register value set to high.
AE Analog Gain Control
AE updates preamp gain register(17h) in order to reach optimum exposure state
AE Windows Weight [AEWINWGT : 72h : cdh]
7 6 5 4 3 2 1 0
Top window 1 1
Center window 0 0
Bottom window 1 1 0
Side window 1
When calculate the average of Y, each window is able to have different weight. Bottom Window in sensor means Top Window in display.
Value `Zro `One `Two `Tri
Weight 1 1/4 1/8 1/16
VEnd
Top(1/16)
VStart
Side(1/4)
Center(1) Bottom(1/16)
Side(1/4)
HStart
HEnd
2005/ 02 / 04 V1.5 - 46 2005 MagnaChip Semiconductor Ltd.
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HV7131RP
Integration Time High [INTH: 73h : 02h]
7 6 5 4 3 2 1 0
Integration Time High [23:16] 0 0 0 0 0 0 1 0
Integration Time Middle [INTM: 74h: 71h]
7 6 5 4 3 2 1 0
Integration Time Middle[15:8] 0 1 1 1 0 0 0 1
Integration Time Low [INTL: 75h: 00h]
7 6 5 4 3 2 1 0
Integration Time Low[7:0] 0 0 0 0 0 0 0 0
Integration time value register defines the time during which active pixel element evaluates photon energy that is converted to digital data output by internal ADC processing. Integration time is equivalent to exposure time of general camera so that integration time need to be increased in dark environment and decreased according to lighting condition. Maximum integration time is register maximum value(224-1) x sensor clock period(80ns, SCF 12.5Mhz @ DCF 25Mhz) = 1.34sec.
AE Target OutDoor [LuTarget1 : 76h : 5ah]
7 6 5 4 3 2 1 0
AE Target OutDoor 0 1 0 1 1 0 1 0
This register defines the target luminance value for AE operation in outdoor.
AE Target InDoor[LuTarget2 : 77h : 5ah]
7 6 5 4 3 2 1 0
AE Target InDoor 0 1 0 1 1 0 1 0
This register defines the target luminance value for AE operation in indoor.
2005/ 02 / 04 V1.5 - 47 2005 MagnaChip Semiconductor Ltd.
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HV7131RP
AE Lock Boundary [AeLockFineBnd : 78h : f6h]
7 6 5 4 3 2 1 0
AE Fine Boundary 1 1 1 1 0
AE Lock Boundary 1 1 0
AE Lock Boundary specifies the displacement of Y Frame Mean value(8eh) from AE Target in which AE goes into LOCK state. With Anti-Banding is enabled, this displacement condition is discarded, and instead AE Speed Unlock Boundary is used as Lock boundary.
AE Fine Boundary specifies the displacement of Y Frame Mean value(8eh) from AE Target in which AE start to tune fine integration time or preamp gain in order to goes into lock state smoothly.
AE Unlock Boundary [AeUnlockBnd : 79h : 2ah]
7 6 5 4 3 2 1 0
AE Unlock Boundary 0 0 1 0 1 0 1 0
AE Unlock Boundary specifies Y Frame Mean displacement from AE Target in which AE goes into UNLOCK state. In this state, integration time increment/decrement speed changes from 2x (integration unit step) to 1x (integration unit step). In anti-banding mode, this boundary is used as lock boundary for exposure control.
AE Anti-Flicker Step High [AeIntStepH : 7ah : 01h]
7 6 5 4 3 2 1 0
reserved 0 0 0 0 0 0
AE Anti-Flicker Step High
0
1
AE Anti-Flicker Step Middle [AeIntStepM : 7bh : 38h]
7 6 5 4 3 2 1 0
AE Anti-Flicker Step High 0 0 1 1 1 0 0 0
2005/ 02 / 04 V1.5 - 48 2005 MagnaChip Semiconductor Ltd.
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AE Anti-Flicker Step Low [AeIntStepL : 7ch : 80h]
7 6 5 4 3 2 1 0
AE Anti-Flicker Step Low 1 0 0 0 0 0 0 0
AE Anti-Banding Step specifies integration time unit value that AE uses when Anti-Banding is enabled. Anti-Banding Step value is resolved by the following equation. Anti-Banding Step Value = Sensor Operation Frequency (SCF) / (2x power line frequency) The default value is set with SCF 12.5Mhz, 50Hz power line, that is, Anti-Banding Step Value = 12.5Mhz / (2 x 50) = 125000d = 1e848h To operate stably, AE Anti-Flicker Step Low [1:0] bits have to `00'. So, Anti-Banding Step Value at HV7131RP is (1e848h & fffffch = 1e848h)
AE Maximum Limit High [AeIntLimitH : 7dh : 09h]
7 6 5 4 3 2 1 0
AE Maximum Limit High 0 0 0 0 1 0 0 1
AE Maximum Limit Middle [AeIntLimitM : 7eh : c4h]
7 6 5 4 3 2 1 0
AE Maximum Limit Middle 1 1 0 0 0 1 0 0
AE Maximum Limit Low [AeIntLimitL : 7fh : 00h]
7 6 5 4 3 2 1 0
AE Maximum Limit Low 0 0 0 0 0 0 0 0
These three registers define the maximum integration time value that is allowed to sensor operation. It is desirable to set the value to multiples of AE Anti-Banding Step to easily operate with Anti-banding mode enabled. The default value is set to 1/8sec with SCF set to 25Mhz 12.5Mhz / 8 = 1,562,500 = 17d784 To operate stably, AE Maximum Limit Low [1:0] bits have to `11'. So, AE Maximum Limit at HV7131RP is (17d784h | 000003h = 17d787h) 2005/ 02 / 04 V1.5 - 49 2005 MagnaChip Semiconductor Ltd.
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HV7131RP
Auto White Balance
Cb/Cr frame mean value is calculated every frame and according to Cb/Cr frame mean values' displacement from Cb/Cr white target point, R/B scaling values for R/B data are resolved.
FFh Cb/Cr AWVB White Pixel Boundary [87h, 88h] AWB Unlock Boundary [86h]
AWB Lock Boundary [85h] 80h Cb/Cr Target [83h, 84h] AWB Lock Boundary [85h]
AWB Unlock Boundary [86h]
Cb/Cr AWB White Pixel 0h Cb/Cr Frame Mean Boundary [87h, 88h]
AWB Mode [AWBMode : 80h : 18h]
7 6 5 4 3 2 1 0
reserved
AtoTstEn
Csp Val En
Awb Enable
AWB Window Enable
AWB Speed
AWB Mode[0]
-
0
0
1
1
0
0
0
AtoTstEn Csp Val En
This value is using at only simulation or test. When this bit set to high, color matrix coefficient [CMA11 ~ CMA33] is used for for color space conversion matrix. And if this bit set to low, the equation from CCIR-601 is used.
2005/ 02 / 04 V1.5 - 50 2005 MagnaChip Semiconductor Ltd.
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Awb Enable
Auto White Balance Control Enabled. AWB is carried out only when satisfying all the following cases. the displacement of Cb/Cr Frame Mean value from AWB Target is larger than AWB Lock Boundary the displacement of Cb/Cr Frame Mean value from AWB Target is smaller than AWB White Pixel Boundary the displacement of the sum of Cb target and Cr target from the sum of average of Cb and Cr is smaller than AWB C Boundary
AWB Window Enable
This bit uses during calculating the average of Cb/Cr value at present frame for AWB. When this bit is HIGH, AWB Window Weight is equal. If not, calculate the average of Cb/Cr using AWB Window Weight.
AWB Speed
AWB Mode[0]
(Fast)11 - 10 - 01 - 00(slow) Set `0'
AWB Windows Weight [AwbWinWgt : 82h : 00h]
7 6 5 4 3 2 1 0
Top window 0 0
Center window 0 0
Bottom window 0 0 0
Side window 0
When calculate the average of Cb/Cr, each window is able to have different weight. Bottom Window in sensor means Top Window in display.
Value `Zro `One `Two `Tri
Weight 1 1/4 1/8 1/16
VEnd
Top(1)
VStart
Side(1)
Center(1) Bottom(1)
Side(1)
HStart
HEnd
2005/ 02 / 04 V1.5 - 51 2005 MagnaChip Semiconductor Ltd.
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HV7131RP
AWB Cb Target Position [CbTarget : 83h : 80h]
7 6 5 4 3 2 1 0
AWB Cb Target Position 1 0 0 0 0 0 0 0
This register defines Cb target frame mean value for AWB operation.
AWB Cr Target Position [CbTarget : 84h : 80h]
7 6 5 4 3 2 1 0
AWB Cr Target Position 1 0 0 0 0 0 0 0
This register defines Cr target frame mean value for AWB operation.
AWB Lock Boundary [AwbLockBnd : 85h : 02h]
7 6 5 4 3 2 1 0
reserved 0 0 0 0 0
AWB Lock Boundary 0 1 0
It specifies Cb/Cr frame mean values' displacement from Cb/Cr Target (83h-84h) value where AWB goes into LOCK state.
AWB Unlock Boundary [AwbUnlockBnd : 86h : 20h]
7 6 5 4 3 2 1 0
AWB Unlock Boundary 0 0 1 0 0 0 0 0
It specifies Cb/Cr frame mean values' displacement from Cb/Cr Target (83h-84h) where AWB is released from LOCK state. AWB operation retains LOCK state unless Cb/Cr frame mean values' displacement value exceeds this boundary. The value should be larger AWB Lock Boundary.
AWB Cb White Pixel Boundary [CbWhiteBnd : 87h : 30h]
7 6 5 4 3 2 1 0
AWB Cb White Pixel Boundary 0 0 1 1 0 0 0 0
When Cb frame mean values' displacement from Cb Target exceeds AWB White Pixel Boundary value, AWB accept frame color as it is and does not try to correct white balance deviation.
2005/ 02 / 04 V1.5 - 52 2005 MagnaChip Semiconductor Ltd.
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AWB Cr White Pixel Boundary [CrWhiteBnd : 88h : 30h]
7 6 5 4 3 2 1 0
AWB Cr White Pixel Boundary 0 0 1 1 0 0 0 0
When Cr frame mean values' displacement from Cr Target exceeds AWB White Pixel Boundary value, AWB accept frame color as it is and does not try to correct white balance deviation.
AWB C Boundary [AwbCBnd : 89h : 30h]
7 6 5 4 3 2 1 0
AWB C Boundary 0 0 1 1 0 0 0 0
In case of the single color which is not a light source, this register uses in order not to operate AWB.
R/B Gain Max [AwbGainMax : 8ah : 3f]
7 6 5 4 3 2 1 0
R/B Gain Max 0 0 1 1 1 1 1 1
The register specifies maximum boundary of AWB R/B gain
R/B Gain Min [AwbGainMin : 8bh : 00]
7 6 5 4 3 2 1 0
R/B Gain Min 0 0 0 0 0 0 0 0
The register specifies minimum boundary of AWB R/B gain
AE State Machine [AeFSM : 8ch : RO]
7 6 5 4 3 2 1 0
AE Mode State
RO RO RO RO RO
AE Lock state
RO RO RO
AE State
Mode This nibble represents the mode where internal Y plane FSM is currently placed among time-gain control, time-only control, or gain-only control modes. "0000" : outdoor exposure control in anti-banding enabled "0001" : gain negative control mode
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"0010" : exposure bidirectional control state "0011" : gain positive control mode "0100" : exposure only control mode "0101" : gain only control mode AE Lock State Y channel FSM status "0000" means that AE Y plane is in lock state "0001" means that AE Y plane is in unlock state "0010" means that AE Y plane is in far state
AWB State Machine [AwbFSM : 8dh : RO]
7 6 5 4 3 2 1 0
reserved
AE/AWB Lock
Cb Lock State
Cr Lock State
RO
RO
RO
RO
RO
RO
RO
RO
AE/AWB Lock
This single status bit indicates that AE and AWB are in lock state for optimum still image capture.
Cb Lock State
Cb channel FSM status. "00" means that AWB Cb plane is in lock state.
Cr Lock State
Cr channel FSM status. "00" means that AWB Cr plane is in lock state
Lu Frame Mean [LuFMean : 8eh : RO]
7 6 5 4 3 2 1 0
Lu Frame Mean
RO RO RO RO RO RO RO RO
The register reports current Y plane frame mean value.
Cb Frame Mean [CbFMean : 8fh : RO]
7 6 5 4 3 2 1 0
Cb Frame Mean
RO RO RO RO RO RO RO RO
The register reports current Cb plane frame mean value.
2005/ 02 / 04 V1.5 - 54 2005 MagnaChip Semiconductor Ltd.
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Cr Frame Mean [CrFMean : 90h : RO]
7 6 5 4 3 2 1 0
Cr Frame Mean
RO RO RO RO RO RO RO RO
The register reports current Cr plane frame mean value.
Anti-Banding Gain Min [KlBndMin : 91h : 14h]
7 6 5 4 3 2 1 0
Anti-Banding Gain Min 0 0 0 1 0 1 0 0
The register specifies the minimum limit to which AE may decrease preamp gain or Y digital gain in order to get optimum exposure value while Anti-Banding Mode is enabled and the following condition is met. AE Lock Boundary < (Y Frame Mean - AE Target) < AE Unlock Boundary.
Anti-Banding Gain Max [KlBndMax : 92h : 3dh]
7 6 5 4 3 2 1 0
Anti-Banding Gain Max 0 0 1 1 1 1 0 1
The register specifies the maximum limit to which AE may increase preamp gain or Y digital gain in order to get optimum exposure value while Anti-Banding Mode is enabled and the following condition is met. AE Lock Boundary < (AE Target - Y Frame Mean) < AE Unlock Boundary.
AWB White Pixel Boundary [AwbWhite : 93h : ffh]
7 6 5 4 3 2 1 0
AWB White Pixel Boundary 1 1 1 1 1 1 1 1
During Cb, Cr frame mean value calculation, AWB discards pixel of which luminance is larger than this register value.
2005/ 02 / 04 V1.5 - 55 2005 MagnaChip Semiconductor Ltd.
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AWB Black Pixel Boundary [AwbBlack : 94h : 00h]
7 6 5 4 3 2 1 0
AWB Black Pixel Boundary 0 0 0 0 0 0 0 0
During Cb, Cr frame mean value calculation, AWB discards pixel of which luminance is smaller than this register value.
AWB Valid Number [AwbNumber : 95h : 02h]
7 6 5 4 3 2 1 0
AWB Valid Number 0 0 0 0 0 0 1 0
AWB update when the number of valid color pixel is larger than (this valid value x 64).
Integration-Scan Plane Offset High [IntScn0fsH : 96h : RO]
7 6 5 4 3 2 1 0
Integration-Scan Offset High
RO RO RO RO RO RO RO RO
Integration-Scan Plane Offset Middle [IntScn0fsM : 97h : RO]
7 6 5 4 3 2 1 0
Integration-Scan Offset Middle
RO RO RO RO RO RO RO RO
Integration-Scan Plane Offset Low [IntScn0fsL : 98h : RO]
7 6 5 4 3 2 1 0
Integration-Scan Offset Low
RO RO RO RO RO RO RO RO
The register represents time offset between integration plane and scan plane. The value should be the same as the value specified by integration time register(73h - 75h).
2005/ 02 / 04 V1.5 - 56 2005 MagnaChip Semiconductor Ltd.
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HV7131RP
Frame Timing
For clear description of frame timing, clocks' acronym and relation are reminded in here again.
< Clock Acronym Definition > MCF : Master Clock Frequency SCF : Sensor Clock Frequency VCF : Video Clock Frequency DCF : Divided Clock Frequency ICF : Image Processing Clock Frequency LCF : Line Clock Frequency
< Clock Frequency Relation > MCF : MCF SCF : DCF/2 DCF : MCF/Clock Division ICF SCF for No Scale Image mode,
SCF/2 for 2 X 2 subsampling mode SCF/4 for 2 X 6 subsampling mode VCF : ICF*2 for 8bit output LCF : 1/(HBLANK Period + HSYNC Period)
HBLANK Period : HBLANK Time register value * (1/SCF) HSYNC Period : HSYNC Active Time
< Frame Time Calculation > Core Frame Time is (IDLE SLOT + Video Height * LCP) and Real Frame Time is resolved as follows. When Integration Time > Core Frame Time, Real Frame Time is (Integration Time + VBLANK * LCP), otherwise is (Core Frame Time + VBLANK * LCP).
1. No Scale Image Timing
No Scale Image Frame Timing Related Parameters
Master Clock Frequency(MCF) Sensor Clock Frequency(SCF) Window Width HBLANK Value VSYNC Mode Output Bus Width Final Video Output Size 20Mhz DCF/2 = 10Mhz 640 208 Line Mode 8bit 640x480 Divided Clock Frequency(DCF) Sensor Clock Period(SCP) Window Height VBLANK Value Line Clock Period(LCP) VGA Video Output Frequency . MCF/1 = 20Mhz 1/10Mhz = 100ns 480 8 848 SCPs SCF * 2 = 20Mhz .
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If Integration Time < Core Frame Time, Real Frame Time is 2 * (208 + 640) SCPs + 480 * (208 + 640) SCPs + 8 * (208 + 640) SCPs = 415520 SCPs = 0.041552sec else Real Frame Time is Integration Time * SCPs + 8 * (208 + 640) SCPs.
HOLD SLOT in frame timing appears only if integration time is larger than core frame time.
IDLE SLOT(2LCPs + (512+HBLANK)*4)
Core Frame Time
HBLANK (208 SCPs)
HSYNC (640 SCPs) Active Data: 640 EA
Video Lines is active every LCP, that is, 480 Video Lines
LCP(848 SCPs)
for 480 LCPs
HOLD SLOT (Integration Time - Core Frame Time) VBLANK[VSYNC] (8 LCPs) Real Frame Time
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480 line data //
HSYNC
HSYNC Idle Slot HBLK 208 SCPs
//
One active video line is equal to one line clock period(LCP) = 848 SCPs VCLK(20Mhz) Y[7:0] Y Cb Y Cr
// //
Y Cb Y
640 SCPs
VSYNC
Hold Slot
VSYNC
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2. 2x2 Subsampling Timing
2 X 2 Subsampling Frame Timing Related Parameters
Master Clock Frequency(MCF) Sensor Clock Frequency(SCF) Window Width HBLANK Value VSYNC Mode Output Bus Width Final Video Output Size 20Mhz DCF/2 = 10Mhz 640 208 Line Mode 8bit 320x240 Divided Clock Frequency(DCF) Sensor Clock Period(SCP) Window Height VBLANK Value Line Clock Period(LCP) SIF Video Output Frequency MCF/1 = 20Mhz 1/10Mhz = 100ns 480 8 848 * 2 SCPs SCF * 1 = 10Mhz
In 2 X 2sub-sampling mode, valid video data is produced every other line, i.e. for 480 LCPs, active video lines are 240. HSYNC active time is equal to HSYNC active time of No Scale Image mode, but video clock frequency is half of No Scale Image mode's to produce half size output in horizontal direction.
IDLE SLOT ((512+HBLANK)*4)
Core Frame Time
1 IDLE LINE (848SCPs)
Video Lines is active every other LCP, that is,
HBLANK (208 SCPs)
HSYNC (640 SCPs) Active Data: 320 EA
240 Video Lines for 480 LCPs
HOLD SLOT (Integration Time - Core Frame Time) VBLANK[VSYNC] (8 LCPs) Real Frame Time
2005/ 02 / 04 V1.5 - 60 2005 MagnaChip Semiconductor Ltd.
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240 line data //
HSYNC
HSYNC Idle Slot HBLK 208 SCPs 1 Idle Line One active video line is equal to one line clock period(LCP) = 848 SCPs
//
320SCPs VCLK=MCLK/4 Y[7:0] Y Cb Y Cr
// //
Y Cb Y
VSYNC
Hold Slot
VSYNC
3. 2 X 6 Subsampling Timing
2 X 6 Subsampling Frame Timing Related Parameters
Master Clock Frequency(MCF) Sensor Clock Frequency(SCF) Window Width HBLANK Value VSYNC Mode Output Bus Width Final Video Output Size 20Mhz DCF/2 = 10Mhz 640 208 Line Mode 8bit 160x120 Divided Clock Frequency(DCF) Sensor Clock Period(SCP) Window Height VBLANK Value Line Clock Period(LCP) QSIF Video Output Frequency MCF/1 = 20Mhz 1/10Mhz = 100ns 480 8 848 * 4 SCPs SCF / 2 = 5Mhz
In 2 X 6 subsampling mode, valid video data is produced every four line, i.e. for 480 LCPs, active video lines are 120. HSYNC active time is equal to HSYNC active time of No Scale Image mode, but video clock frequency is a quarter of No Scale Image mode's to produce a quarter size output in horizontal direction.
2005/ 02 / 04 V1.5 - 61 2005 MagnaChip Semiconductor Ltd.
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HV7131RP
Core Frame
IDLE SLOT ( (512+HBLANK)*4)
Time
Video data is active at last 1 LCP
3 IDLE LINES (3 * 848 SCPs)
period of every 4 LCPs period, that is,
HBLANK (208 SCPs)
HSYNC (640 SCPs) Active Data: 160 EA HOLD SLOT (Integration Time - Core Frame Time) VBLANK[VSYNC] (8 LCPs)
120 Video Lines for 480 LCPs
Real Frame Time
120 line data //
HSYNC
HSYNC Idle Slot HBLK 208 SCPs 3 Idle Line One active video line is equal to one line clock period(LCP) = 848 SCPs
//
160SCPs VCLK=MCLK / 8 Y[7:0] Y Cb Y Cr
// //
Y Cb Y
VSYNC
Hold Slot
VSYNC
2005/ 02 / 04 V1.5 - 62 2005 MagnaChip Semiconductor Ltd.
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HV7131RP
Anti-Banding Configuration
For Anti-Banding mode to work correctly, the following registers should be configured to the appropriate values.
AE Mode AE Anti-Banding Step AE Integration Time Limit
70h 7a-7ch 7d-7fh
Anti-Banding Enable[7] SCF / (2 x power line frequency) The value should be multiples of AE Anti-Banding Step
When Anti-Banding is enabled, AE initializes Integration Time registers[73-75h] to 4 x Anti-Banding Step value[7a-7ch], and integration increment/decrement amount is set to Anti-Banding Step value in order to remove anti-banding noise caused by intrinsic energy waveform of light sources. Banding noise is inherent in CMOS image sensor that adopts rolling shutter scheme for image acquisition.
Data Output Timing and Interface
14 ns ~ 15 ns M CLK
V C LK
HSYNC
Y [7 :0 ]
X
Y0
Y1
Y2
4ns ~ 5ns
As specified in the above data output timing diagram, the timing margin between video clock pin (VCLK) and data pins (Y[7:0]) is about 4ns ~ 5ns. This margin may be sufficient or not according to how much video clock and data pins are delayed internally in the backend chip, respectively. To safely latch the data output in the backend chip, it is recommended that data be latched at negative edge of VCLK.
2005/ 02 / 04 V1.5 - 63 2005 MagnaChip Semiconductor Ltd.
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HV7131RP
Output Data according to Video Mode
Output Data according to Video Mode is controlled by configuring Sensor Control A[01h]. Configurable options are specified again for your reference.
< Video Mode Setting >
Row SubSampling
YCbCr 4:2:2 OUTFMT[6:4] = 6h
RGB 5:6:5 OUTFMT[6:4] = 7h Support Support
Bayer SCTRC[7] = 1
VGA(640x480) SCTRA[2:0] = 0h or 3h QVGA(320x240) SCTRA[2:0] = 2h QQVGA(160x120 ) SCTRA[2:0] = 1h CIF(236x288) SCTRA[2:0] = 8h or Bh QCIF(178x144) SCTRA[2:0] = Ah
ISP(SSSel = 0) Bayer(SSSel = 1)
Support Support
None Support
ISP(SSSel = 0) Bayer(SSSel = 1) ISP(SSSel = 0) Bayer(SSSel = 1)
Support Support Support Support
Support Support Support Support
None Support None Support
ISP(SSSel = 0) Bayer(SSSel = 1)
Support Support
Support Support
Not Support Not Support
ISP(SSSel = 0) Bayer(SSSel = 1)
Support Support
Support Support
Not Support Not Support
2005/ 02 / 04 V1.5 - 64 2005 MagnaChip Semiconductor Ltd.
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HV7131RP
< Video Mode Setting >
Output Format
Sensor Control A [0x01] (640 x 480) 0x00, 0x02 0x01 0x08, 0x0a 0x04, 0x07 0x06 0x05 0x0c, 0x0f 0x0e 0x00, 0x03 0x02 0x01 0x08, 0x0b 0x0a 0x04, 0x07 0x06 0x05 0x0c, 0x0f 0x0e 0x04, 0x07 0x06 0x05 0x0b 0x03
Sensor Control C [0x05] 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x80 0x80 0x80
Output Format [0x31] 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x00 0x00 0x00
VGA YCbCr422 ISP Subsampling
QVGA (320 x 240) QQVGA (160 x 120) CIF QCIF VGA (356 x 288) (178 x 144) (640 x 480)
YCbCr422 Bayer Sub-sampling
QVGA (320 x 240) QQVGA (160 x 120) CIF QCIF VGA (356 x 288) (178 x 144) (640 x 480)
RGB565 ISP Subsampling
QVGA (320 x 240) QQVGA (160 x 120) CIF QCIF VGA (356 x 288) (178 x 144) (640 x 480)
RGB565 Bayer Sub-sampling
QVGA (320 x 240) QQVGA (160 x 120) CIF QCIF (356 x 288) (178 x 144) (640 x 480)
Bayer sampling
Sub-
VGA
QVGA (320 x 240) QQVGA (160 x 120)
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HV7131RP
Output timings for general configurations are described below. Slot named as "X" means that it is has no meaningful value and should be discarded.
No Scale Image Mode or Sub-sampling (2x2, 2x6) Mode
1. YCbCr 4:2:2 Mode or Sub-sampling (2x2, 2x6) Mode Register bit configurations Sensor Control A : No Scale Mode or Sub-sampling Mode Output Format : 8bit Output, Y First, U First.
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HV7131RP
VCLK
HSYNC No Scale Mode Video Clock & Output Data
CLK Y[7:0]
X X Y0 Cb0 Y1 Cr0 Y2 Cb1 Y3 Cr1 Y4 Cb2 Y5 Cr2 Y5 Cb3 Y6 Cr3
C[7:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
2 X 2 Video Clock & Output Data
CLK Y[7:0]
X Y0 Cb0 Y1 Cr0 Y2 Cb1 Y3 Cr1
2 X 6 Video Clock & Output Data
CLK Y[7:0]
X Y0 Cb0 Y1 Cr0
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2. RGB565 Mode or Sub-sampling (2x2, 2x6) Mode
Register bit configurations Sensor Control A : No Scale Mode or Sub-sampling Mode Output Format : 8bit Output, Y First, U First and RGB565 enable.
VCLK
HSYNC No Scale Mode Video Clock & Output Data
CLK Y[7:0]
X X RG0 GB0 RG1 GB1 RG2 GB2 RG3 GB3 RG4 GB4 RG5 GB5 RG6 GB6 RG7 GB7
{R0[7:3] G0[7:5]}
{G0[4:2] B0[7:3]}
2 X 2 Video Clock & Output Data
CLK Y[7:0]
X RG0 GB0 RG2 GB2 RG4 GB4 RG6 GB6
2 X 6 Video Clock & Output Data
CLK Y[7:0]
X RG0 GB0 RG4 GB4
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HV7131RP
3. Bayer Mode or Sub-sampling (2x2, 2x6) Mode Register bit configurations Sensor Control A : Bayer Mode( SSSel enable) or Sub-sampling Mode Output Format : 8bit Output, Y First, U First
VCLK HSYNC Bayer Mode Video Clock & Output Data Y[7:0] Even Line Y[7:0] Odd Line X X B G G R B G G R B G G R B G G R B G G R B G
2 X 2 Video Clock & Output Data HSYNC
Y[7:0] Even Line Y[7:0] Odd Line
X X
B G
G R
B G
G R
B G
G R
B G
G R
B G
G R
B G
2 X 6 Video Clock & Output Data 6 Line Data HSYNC //
Y[7:0] Even Line Y[7:0] Odd Line
X X
B G
G R
B G
G R
B G
G R
B G
G R
B G
G R
B G
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HV7131RP
CIF or QCIF Mode
1. YCbCr 4:2:2 with 8bit Output Register bit configurations Sensor Control A : No Scale Mode and CIF Mode Output Format : 8bit Output, Y First, U First CIF HSYNC VCLK Y[7:0] QCIF HSYNC VCLK Y[7:0]
Y0 Cb0 Y1 Cr0 Y2 Cb1 Y3 Cr1 // Y12 Cb6 Y13 Cr6 Y0 Cb0 Y1 Cr0 Y2 Cb1 Y3 Cr1 // Y12 Cb6 Y13 Cr6
2. RGB565 with 8bit Output Register bit configurations Sensor Control A : No Scale Mode or CIF Mode Output Format : 8bit Output, Y First, U First and RGB565 enable.
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CIF HSYNC VCLK Y[7:0] QCIF HSYNC VCLK Y[7:0]
RG0 GB0 RG1 GB1 RG2 GB2 RG3 GB3 // RG6 GB6 RG7 GB7 RG0 GB0 RG1 GB1 RG2 GB2 RG3 GB3 // RG12 GB12 RG13 GB13
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I2C Chip Interface
Register Write Sequences
One Byte Write
S *1
22H *2
A *3
01H *4
A *5
03H *6
A *7
P *8
Set "Sensor Control A" register into Window mode *1. Drive: I2C start condition *2. Drive: 22H(001_0001 + 0) [device address + R/W bit] *3. Read: acknowledge from sensor *4. Drive: 01H [sub-address] *5. Read: acknowledge from sensor *6. Drive: 03H [Video Mode : CIF *7. Read: acknowledge from sensor *8. Drive: I2C stop condition
Multiple Byte Write using Auto Address Increment S *1
22H *2
A *3
6aH *4
A *5
51H *6
A *7
61H *8
A *9
P *10
Set "AE Integration Step High/Low" register as 5161H with auto address increment *1. Drive: I2C start condition *2. Drive: 22H(001_0001 + 0) [device address + R/W bit] *3. Read: acknowledge from sensor *4. Drive: 6aH [sub-address] *5. Read: acknowledge from sensor *6. Drive: 51H [AE Integration Step High] *7. Read: acknowledge from sensor *8. Drive: 61H [AE Integration Step Low] *9. Read: acknowledge from sensor *10. Drive: I2C stop condition
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Register Read Sequence
S
*1
22H
*2
A
*3
50H
*4
A
*5
S
*6
23H
*7
A
*8
Data of 50H
*9
A
P
*10 *11
Read "Reset Level Control" register from HV7131RP *1. Drive: I2C start condition *2. Drive: 22H(001_0001 + 0) [device address + R/W bit(be careful. R/W=0)] *3. Read: acknowledge from sensor *4. Drive: 50H [sub-address] *5. Read: acknowledge from sensor *6. Drive: I2C start condition *7. Drive: 23H(001_0001 + 1) [device address + R/W bit(be careful. R/W=1)] *8. Read: acknowledge from sensor *9. Read: Read "Reset Level Control Value" from sensor
*10. Drive: acknowledge to sensor. If there is more data bytes to read, SDA should be driven to low and data read states(*9, *10) is repeated. Otherwise SDA should be driven to high to prepare for the read transaction end. *11. Drive: I2C stop condition
AC/DC Characteristics
Absolute Maximum Ratings
Symbol Vdpp Vapp Vipp Top Tst Parameter Digital supply voltage Analog supply voltage Input signal voltage Operating Temperature Storage Temperature Units Volts Volts Volts C C Min. -0.3 -0.3 -0.3 -10 -30 Max. 7.0 7.0 7.0 50 80
Caution: Stresses exceeding the absolute maximum ratings may induce failure.
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DC Operating Conditions
Symbol Vdd Vih Vil Voh Vol Ioh Iol Ta Parameter Internal operation supply voltage Input voltage logic "1" Input voltage logic "0" Output voltage logic "1" Output voltage logic "0" Output High Current Output Low Current Ambient operating temperature Units Volt Volt Volt Volt Volt mA mA Celsius -10 Min. 2.6 2.0 0 2.15 0.4 -4 4 50 Max. 3.0 3.0 0.8 6.5 6.5 60 60 60 60 at Ioh = -1mA Load[pF] Notes
AC Operating Conditions
Symbol MCLK SCK Parameter Main clock frequency I2C clock frequency Max Operation Frequency 25 400 Units MHz KHz Notes 1,2 3
1. MCLK may be divided by internal clock division logic for easy integration with high speed video codec system. 2. Frame Rate : 30 frames/sec at 25Mhz, HBLANK = 208, VBLANK = 8 3. SCK is driven by host processor. For the detail serial bus timing, refer to I2C chip interface section
Output AC Characteristics
All output timing delays are measured with output load 60[pF]. Output delay includes the internal clock path delay and output driving delay that changes in respect to the output load, the operating environment, and a board design. Due to the variable valid time delay of the output, video output signals Y[7:0], C[7:0], HSYNC, and VSYNC may be latched in the negative edge of VCLK for the stable data transfer between the image sensor and video codec.
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V C LK
HSY NC
Y /C [7:0]
X
D ata 0
D ata 1
D a ta 2
D a ta 3
4 ns ~ 5n s
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I2C Bus Timing
stop
start
start
stop
SDA
tr tbuf tlow tf thd;sta
SCK
thd;sta
thd;dat
thigh
tsu;dat
tsu;sta
tsu;sto
Parameter SCK clock frequency Time that I2C bus must be free before a new transmission can start Hold time for a START LOW period of SCK HIGH period of SCK Setup time for START Data hold time Data setup time Rise time of both SDA and SCK Fall time of both SDA and SCK Setup time for STOP Capacitive load of SCK/SDA
Symbol f sck tbuf thd;sta tlow thigh tsu;sta thd;dat tsu;dat tr tf tsu;sto Cb
Min. 0 1.2 1.0 1.2 1.0 1.2 100 250 1.2 -
Max. 400 250 300 -
Unit KHz us us us us us ns ns ns ns us pf
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Electro-Optical Characteristics
Parameter Sensitivity Dark Signal Output Saturation Signal Units mV / luxsec mV mV Min. Typical 2200 12 780 Max. Note Green Pixel 1/10" , 60
- Color temperature of light source: 3200K / IR cut-off filter (CM-500S, 1mm thickness) is used.
Soldering Infrared(IR) / Convection solder reflow condition Parameter Peak Temperature Range Note: Units Celsius Min. Typical 230 Max. 240 Note 1)
1) Time within 5 Celsius of actual peak temperature, 10sec
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CLCC Package Specification
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MagnaChip Semiconductor Ltd.
* Contact Point *
CIS Marketing Team
15Floor, MagnaChip Youngdong Bldg. 891 Daechi-Dong Kangnam-Gu Seoul 135-738 Republic of Korea Tel: 82-2-3459-3374 Fax: 82-2-3459-5580 E-mail : jungjin.jeong@MagnaChip.com
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